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AR# 11008

4.1i CORE Generator - Asynchronous FIFO - MAP "ERROR:Pack:679 - Unable to obey design constraints"


Keywords: FIFO, CORE Generator, COREGen, Virtex-II, RPM, pack, 679, MACRONAME, carry

Urgency: Standard

General Description:
My Virtex/Virtex-II design contains the Asynchronous FIFO (v2, 3, and 4) that was generated with RPMs. The following error occurs in MAP if I use the "-u" switch:

"ERROR:Pack:679 - Unable to obey design constraints (MACRONAME = u0_u0/fifocore/control/rd_blk, RLOC = X2Y0), which require the combination of the following symbols into a single slice component:
MUXCY symbol "u0_u0/BU421" (Output Signal = u0_u0/BU421/O)
FLOP symbol "u0_u0/BU422" (Output Signal = u0_u0/N11670)
LUT symbol "u0_u0/BU417" (Output Signal = u0_u0/N12596)
MUXCY symbol "u0_u0/BU418" (Output Signal = u0_u0/BU418/O)
FLOP symbol "u0_u0/BU419" (Output Signal = u0_u0/N11671)

The carry muxes are not connected in the required manner. Please correct the design constraints accordingly."


The CORE Generator Asynchronous FIFO and a number of the underlining cores do not properly handle the MAP "-u" option when using RPMs. The above MAP error is seen when the following two conditions exist:

1. The Asynchronous FIFO core was generated with RPM;
2. MAP is run with "-u" switch.

No MAP error is issued if one of the circumstances above does not exist; to prevent this error, avoid using one of the above conditions.
AR# 11008
Date 09/11/2003
Status Archive
Type General Article