AR# 11011: 3.1i CPLD 9500/XL - Latches in CPLD hardware exhibit strange behavior when timing simulation passes.
3.1i CPLD 9500/XL - Latches in CPLD hardware exhibit strange behavior when timing simulation passes.
Keywords: 9500, CPLD, latch, JEDEC, transparent
General Description: When using a latch in a 9500 design, the timing simulation is correct; however, on the device, the latch clears for no apparent reason.
Latches are often implemented by the fitter with the asynchronous clear and preset of a register. When the JEDEC generation occurs (Hprep6), the clock input of the register is erroneously connected to Global Clock Line 2. When this clock line toggles, the register clocks in a "0" because the data line to the register is unconnected -- this resets the flip-flop.