Is there a limit to the total delay of the feedback path?
If I wish to align internal and board clock, is there a guideline regarding how much delay the CLKDLL/DCM can withstand?
There is no limit on the total delay of the feedback path, but there is a limit on how much the delay of the feedback path can vary across environmental conditions. This is specified for Virtex-II as CLKFB_DELAY_VAR_EXT= +/- 1ns.
(This value also applies for Virtex and Virtex-E.)