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  3. AR# 1104: MAKEBITS TIE--Should all designs be tied?
  4. AR# 11041: Virtex/E/II, DLL - Is there a limit to the total delay of the feedback path to CLKFB? (CLKFB_DELAY_VAR_EXT)

AR# 11041

Virtex/E/II, DLL - Is there a limit to the total delay of the feedback path to CLKFB? (CLKFB_DELAY_VAR_EXT)

Description

Is there a limit to the total delay of the feedback path? 

 

If I wish to align internal and board clock, is there a guideline regarding how much delay the CLKDLL/DCM can withstand?

Solution

There is no limit on the total delay of the feedback path, but there is a limit on how much the delay of the feedback path can vary across environmental conditions. This is specified for Virtex-II as CLKFB_DELAY_VAR_EXT= +/- 1ns. 

 

(This value also applies for Virtex and Virtex-E.)

AR# 11041
Date 05/14/2014
Status Archive
Type General Article