AR# 11044

3.1i HDL Bencher - Configuration statements are handled incorrectly

Description

Keywords: configuration, statement, HDL, Bencher

Urgency: Standard

General Description:
When HDL Bencher is used with a design that contains configuration statements, a configuration statement must be modified whenever a functional or timing simulation is performed.

For example:

"for all : decoder_top use configuration work.decoder_cfg;
end for; "

will not be copied over to the testbench if it is contained in the original design file.

If multiple cores are used, similar lines must be repeated. This is not only a tedious process to perform, but it can also cause other problems.

Solution

In the 4.1i software, configuration statements were removed, as the VHDL flow more closely resembles the Verilog flow.

As a result, there will be no changes to the HDL Bencher.
AR# 11044
Date 08/15/2002
Status Archive
Type General Article