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AR# 11045

3.1i Virtex-II DCM - Large skew seen between two outputs of the DCM


Keywords: Virtex, NGDAnno, CLKFX, CLK0

Urgency: Standard

General Description:
I have a Virtex-II design that uses a DCM, and I have created a back-annotated timing simulation file. When using the SDF file generated, I see skew between two outputs of the DCM (such as CLK0 and CLKFX). Both of these signals are going through BUFGs, and the handbook says they should be in phase. What is wrong?


One possibility is that the BUFGs are not being placed together on the same edge of the chip. Open the design in FPGA Editor, and look for clock nets being routed across the chip to a BUFG on the opposite edge.

If this is the case, make sure that the BUFGs that are driven by the same DCM are LOC'd on the same edge of the chip as the DCM.

This is fixed in the ISE 4.1i.
AR# 11045
Date 08/26/2002
Status Archive
Type General Article