AR# 11067: ModelSim Simulations: Input and Output clocks of the DCM and CLKDLL models do not appear to be de-skewed (VHDL, Verilog)
ModelSim Simulations: Input and Output clocks of the DCM and CLKDLL models do not appear to be de-skewed (VHDL, Verilog)
Keywords: timing, run, internal
When I run a timing simulation with ModelSim, the clocks from the DCM and CLKDLL models do not appear to be de-skewed. If the DCM and CLKDLL are supposed to line up the internal clock with the input clock, why does this occur?
First, make sure that the correct signals are being compared. After the DCM or CLKDLL is locked, the clock at the input port should align with the clock at the input to a register. The clock at the input port should not align with the clock from the DCM or CLKDLL, or with the clock from the global buffer.
When the correct signals are compared, the ModelSim Wave window still displays a small amount of clock skew between the clocks. The simulation is correct, but the waveforms are not shown as expected. The reason for this apparent skew is the way that the delays in the SDF are handled by ModelSim.
The SDF annotates the CLOCK PORT delay on the X_FF components; however, the simulator displays the clock signal before taking this delay into account. If this CLOCK PORT delay on the X_FF is added to the internal clock signal, it lines up with the input port clock (within the device specifications in the data sheet) in the waveform viewer. Again, the simulation is functionally correct. This is only an issue with the way in which the waveforms are displayed in ModelSim.
If you require the waveforms to be displayed correctly, there is a temporary way to work around this in the Xilinx ISE design tools by adding an the environment variable "NLW_ADD_ROUTEDLY_BUFFER" and setting its value to 1. This results in the addition of an extra buffer before every clock input port. The delay that was previously annotated on the input port of the register is now moved to this extra buffer. When you view the clock in the register, it is now properly aligned with the input clock. However, this increases the netlist size, increases simulator memory usage, and slows down simulation. As a result, Xilinx does not recommended the use of the environment variable.
Model Technology plans to enhance the ModelSim Waveform Viewer to display the delays correctly in a future software version.