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  3. AR# 11074: SYNPLIFY, Virtex-II - Instantiated DCM becomes DCM_1 in Synplicity netlist.

AR# 11074

SYNPLIFY, Virtex-II - Instantiated DCM becomes DCM_1 in Synplicity netlist.

Description

Keywords: Synplicity, Synplify, DCM, DCM_1, netlist

Urgency: Standard

Problem Description:
I have instantiated a DCM in my Synplicity netlist and synthesized the design. When I
try to implement it, NGDBuild gives me an unexpanded regarding a component of type
"DCM_1" as follows:

"ERROR:NgdBuild:432 - logical block 'DCM0' with type 'DCM_1' is unexpanded."

Solution

See (Xilinx Solution 11095) for a DCM instantiation example.

This happens if "defparam" is used to pass DCM attribute in Verilog. To fix
this, use "synthesis xc_props" to pass the attribute to DCM.

Use "synthesis translate_off" and "synthesis translate_on" to comment out
defparam during synthesis.
AR# 11074
Date 04/20/2007
Status Archive
Type General Article
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