General Description: This answer record addresses known issues in 32i_ip_update3 (also referred to as "D_IP3").
GENERAL KNOWN ISSUES
The D_IP3 IP update is only compatible with Xilinx CORE Generator v3.1i, which is included with Alliance v3.1i, Foundation v3.1i, and Foundation ISE v3.1i software. This IP update is also compatible with v3.2i , v3.3i, and subsequent releases. This IP update should not be used with any other versions of CORE Generator (such as v2.1i or earlier).
D_IP3 update is cumulative; therefore, previous IP updates are not required. If you are a Workstation user and have already installed 3.1i_ip_update1 (D_IP1) on your system, your system administrator may need to change the permissions on your current CORE Generator installation before you install the D_IP3 update. This can be done by using the following command:
1. When large Distributed Memory (C_DIST_MEM_V4_0) cores are generated, there is a possibility that the design will fail when it passes through BitGen. This failure occurs because PAR does not correctly insert buffers to signals that have very large fanouts. -- Please see (Xilinx Answer 11103).
2. The placer rejects valid Virtex-II DPRAM macros, including some defined by CORE Generator. The errors posted begin with the message:
"ERROR:Place:1809 - RPM "TCP_FPGA_CORE_INST/DPR_32X16_INST/ v2_dpr_32X16_INST/hset" may not be placed in such a way that it can be routed."
1. When using Xilinx CORE Generator Multiplier v3_0 with Type set to "sequential," the correct output result may not be given if the output width is less than the minimum required width. -- Please see (Xilinx Answer 10964).
2. When compiling Multiplier v3_0 VHDL behavioral model (mult_gen_v3_0.vhd) with simulators other than ModelSim (MTI), errors may occur during the compilation. -- Please see (Xilinx Answer 11161).
32-Point Parameterizeable FFT v1_0
A Verilog behavioral simulation model is NOT available for this core; however, CORE Generator will output a .veo (instantiation) file without any error/warning. -- Please see (Xilinx Answer 11155).
Direct Digital Synthesizer v3_0
When using the DDS v3.0, targeting a Virtex-II, and choosing to implement using block ROM, an error message may be reported when a core is generated. -- Please see (Xilinx Answer 11203).
Reed Solomon Decoder/Encoder v1_0
1. Starting CORE Generator after installing the D_IP3 update may cause the following errors:
"ERROR: Could not locate Project core xilinx_reed-solomon_decoder|xilinx|virtex+xc4000+spartan|1.0 ERROR: Could not locate Project core xilinx_reed-solomon_encoder|xilinx|virtex+xc4000+spartan|1.0"
2. The Xilinx Reed Solomon Encoder and Decoder that is currently available with 3.xi_ip_update3 is v1_0. The data sheet will indicate v2_0; however, the available core is v1_0, and it does not support Virtex-II architecture. -- Please see (Xilinx Answer 11239).