AR# 11095

SYNPLIFY - How do I instantiate the DCM and pass the attributes in HDL? (VHDL/Verilog)

Description

General Description:

How do I instantiate and pass the DCM attribute in VHDL/Verilog?

(NOTE: This Answer Record contains DCM examples; CLKDLL users may use the same method to pass attributes on CLKDLL.)

Solution

VHDL Example

library IEEE;

library unisim;

use IEEE.std_logic_1164.all;

use unisim.vcomponents.all;

entity clock_block is

port (

CLK_PAD : in std_logic;

RST_DLL : in std_logic;

CLK_out : out std_logic;

LOCKED : out std_logic

);

end clock_block;

architecture STRUCT of clock_block is

signal CLK, CLK_int, CLK_dcm : std_logic;

attribute DLL_FREQUENCY_MODE : string;

attribute DLL_FREQUENCY_MODE of U2: label is "HIGH";

component IBUFG

port (

I : in std_logic;

O : out std_logic);

end component;

component BUFG

port (

I : in std_logic;

O : out std_logic);

end component;

component DCM is

port (

CLKFB : in std_logic;

CLKIN : in std_logic;

DSSEN : in std_logic;

PSCLK : in std_logic;

PSEN : in std_logic;

PSINCDEC : in std_logic;

RST : in std_logic;

CLK0 : out std_logic;

CLK90 : out std_logic;

CLK180 : out std_logic;

CLK270 : out std_logic;

CLK2X : out std_logic;

CLK2X180 : out std_logic;

CLKDV : out std_logic;

CLKFX : out std_logic;

CLKFX180 : out std_logic;

LOCKED : out std_logic;

PSDONE : out std_logic;

STATUS : out std_logic_vector

(7 downto 0));

end component;

begin

U1 : IBUFG port map ( I => CLK_PAD, O => CLK_int);

U2 : DCM port map (

CLKFB => CLK,

CLKIN => CLK_int,

DSSEN => '0',

PSCLK => '0',

PSEN => '0',

PSINCDEC => '0',

RST => RST_DLL,

CLK0 => CLK_dcm,

LOCKED => LOCKED);

U3 : BUFG port map (I => CLK_dcm, O => CLK);

CLK_out <= CLK;

end architecture STRUCT;

Verilog Example

module clock_top (clk_pad, rst_dll, clk_out, locked);

input clk_pad, rst_dll;

output clk_out, locked;

wire clk, clk_int, clk_dcm;

IBUFG u1 (.I (clk_pad), .O (clk_int));

DCM u2 (.CLKFB (clk),

.CLKIN (clk_int),

.DSSEN (1'b0),

.PSCLK (1'b0),

.PSEN (1'b0),

.PSINCDEC (1'b0),

.RST (rst_dll),

.CLK0 (clk_dcm),

.LOCKED (locked)) /* synthesis

DLL_FREQUENCY_MODE="HIGH" */;

BUFG u3(.I (clk_dcm), .O (clk));

assign clk_out = clk;

endmodule // clock_top

Verilog Example - with the "defparam" statement

(NOTE: When "xc_props" is used for multiple attributes [as in this example], all attributes must be entered as a single line without carriage returns.)

module DCM_TEST(

clock_in,

clock_out,

clock_with_ps_out,

reset

);

input clock_in;

output clock_out;

output clock_with_ps_out;

output reset;

wire low;

wire high;

wire dcm0_locked;

wire dcm1_locked;

wire reset;

wire clk0;

wire clk1;

assign low = 1'b0;

assign high = 1'b1;

assign reset = !(dcm0_locked & dcm1_locked);

IBUFG CLOCK_IN (

.I(clock_in),

.O(clock)

);

DCM DCM0 (

.CLKFB(clock_out),

.CLKIN(clock),

.DSSEN(low),

.PSCLK(low),

.PSEN(low),

.PSINCDEC(low),

.RST(low),

.CLK0(clk0),

.CLK90(),

.CLK180(),

.CLK270(),

.CLK2X(),

.CLK2X180(),

.CLKDV(),

.CLKFX(),

.CLKFX180(),

.LOCKED(dcm0_locked),

.PSDONE(),

.STATUS()

)

/*synthesis xc_props="DLL_FREQUENCY_MODE = LOW,

DUTY_CYCLE_CORRECTION = TRUE,

STARTUP_WAIT = TRUE,DFS_FREQUENCY_MODE = LOW,

CLKFX_DIVIDE = 1,CLKFX_MULTIPLY = 1,

CLK_FEEDBACK = 1X,CLKOUT_PHASE_SHIFT = NONE,

PHASE_SHIFT = 0" */;

BUFG CLK_BUF0(

.O(clock_out),

.I(clk0)

);

DCM DCM1 (

.CLKFB(clock_with_ps_out),

.CLKIN(clock),

.DSSEN(low),

.PSCLK(low),

.PSEN(low),

.PSINCDEC(low),

.RST(low),

.CLK0(clk1),

.CLK90(),

.CLK180(),

.CLK270(),

.CLK2X(),

.CLK2X180(),

.CLKDV(),

.CLKFX(),

.CLKFX180(),

.LOCKED(dcm1_locked),

.PSDONE(),

.STATUS()

) /*synthesis xc_props="DLL_FREQUENCY_MODE=LOW,

DUTY_CYCLE_CORRECTION = TRUE,

STARTUP_WAIT = TRUE,

DFS_FREQUENCY_MODE = LOW,CLKFX_DIVIDE =1,

CLKFX_MULTIPLY = 1,CLK_FEEDBACK =1X,

CLKOUT_PHASE_SHIFT = FIXED,PHASE_SHIFT = 0" */;

//Note: Don't insert any carriage return between the attributes above.

BUFG CLK_BUF1(

.O(clock_with_ps_out),

.I(clk1)

);

// The following defparam statements are for simulation only

//synthesis translate_off

defparam DCM0.DLL_FREQUENCY_MODE = "LOW";

defparam DCM0.DUTY_CYCLE_CORRECTION = "TRUE";

defparam DCM0.STARTUP_WAIT = "TRUE";

defparam DCM0.DFS_FREQUENCY_MODE = "LOW";

defparam DCM0.CLKFX_DIVIDE = 1;

defparam DCM0.CLKFX_MULTIPLY = 1;

defparam DCM0.CLK_FEEDBACK = "1X";

defparam DCM0.CLKOUT_PHASE_SHIFT = "NONE";

defparam DCM0.PHASE_SHIFT = "0";

defparam DCM1.DLL_FREQUENCY_MODE = "LOW";

defparam DCM1.DUTY_CYCLE_CORRECTION = "TRUE";

defparam DCM1.STARTUP_WAIT = "TRUE";

defparam DCM1.DFS_FREQUENCY_MODE = "LOW";

defparam DCM1.CLKFX_DIVIDE = 1;

defparam DCM1.CLKFX_MULTIPLY = 1;

defparam DCM1.CLK_FEEDBACK = "1X";

defparam DCM1.CLKOUT_PHASE_SHIFT = "FIXED";

defparam DCM1.PHASE_SHIFT = "0";

//synthesis translate_on

endmodule // DCM_TEST

AR# 11095
Date 12/15/2012
Status Active
Type General Article