AR# 11102

Description

General Description:

When I instantiate the IBUF/OBUF_PCIX66_3, NGDBuild issues the following messages:

"ERROR: NgdBuild:455 - logical net 'a_IBUF' has multiple drivers.

WARNING: NgdBuild:463 - input pad net 'a_IBUF' has an illegal input buffer.

ERROR: NgdBuild:466 - input pad net 'a_IBUF' has illegal connection.

ERROR: NgdBuild:467 - output pad net 'b_OBUF' has an illegal buffer."

(XST is inserting extra I/O buffer components.)

NOTE: This problem is fixed in the latest 4.1i Service Pack, available at:

http://support.xilinx.com/support/techsup/sw_updates

The first service pack containing the fix is 4.1i Service Pack 1.

Solution

If an OBUF_PCIX66_3 is instantiated, then you must disable I/O insertion. If only the IBUF_PCIX66_3 is used, add the "clock_buffer=none" attribute to the input port of the your VHDL code as folllows:

library ieee;

use ieee.std_logic_1164.all;

entity ibuf_test is

port (d, clk : in std_logic;

q : out std_logic);

end entity;

architecture ibuf_test_arch of ibuf_test is

component IBUF_PCIx66_3 is

port (i : in std_logic;

o : out std_logic);

end component;

signal d_i : std_logic;

attribute clock_buffer : string;

attribute clock_buffer of d : signal is "none";

begin

u1 : IBUF_PCIx66_3 port map(d, d_i);

process (clk) begin

if clk'event and clk = '1' then

q<=d_i;

end if;

end process;

end architecture;

If an OBUF_PCIX66_3 is instantiated, you must disable I/O insertion. If only the IBUF_PCIX66_3 is used, add the "clock_buffer=none" attribute to the input port of the your VHDL code as follows:

module pciibuf(d, clk, q);

input d, clk;

output q;

wire d_i;

reg q;

IBUF_PCIX66_3 u1 (.I(d), .O(d_i));

//synthesis attribute clock_buffer of d is "none"

always@(posedge clk) q <= d_i;

endmodule