General Description: I have a large CORE Generator module (such as Distributed Memory v4) in my design, and I encounter the following error when running BitGen:
ERROR:DesignRules:475 - Netcheck: Improper routing. Signal INT_DPRA<0> is routed with far too many unbuffered connections. This net must be rerouted. To resolve this error, please consult the answers database at http://support.xilinx.com
This is actually a routing issue, not a BitGen issue. The problem is detected by BitGen because DRC is first run by default during BitGen. The problem is flagged when the router strings together too many unbuffered resources to make a connection. 3.1i Service Pack 8 fixes a specific known problem whereby the router sometimes introduces this problem in certain CORE Generator modules.
NOTE: This issue affects the Virtex, Virtex-E and Spartan-II device architectures.