The GCLKxS and GCLKxP are located on opposite sides of the device. Is this correct?
The pairs are not paired up according to the names of the GCLKs.
The correct pairs are listed in the following:
Virtex-II Platform FPGA User Guide -> Design Considerations -> Using Global Clock Networks -> Clock Distribution Resources -> Primary and Secondary Global Multiplexers:
Table 2-2 lists the Top Clock Multiplexer Pairs
Table 2-3 lists the Bottom Clock Multiplexer Pairs
The information in the on-line documentation agrees with the pin-outs. For example, 5P is paired with 4S. In the pin-out of the FF896 package, 5P is Pin C17, and 4S is Pin C16.