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3.1i CPLD XC9500 Hitop - Illegal optimization causes inputs to be removed or incorrect logic to be implemented.
Keywords: Hitop, 9500, WebPACK, ISE, optimization
A CPLD 9500 design is being illegally optimized during Hitop. The design entry can be in schematic, VHDL, Verilog or ABEL.
The name of the entity or module -- and, hence, the name of the top-level netlist -- contains a keyword "NOR" in its name (e.g., "north_design").
This keyword is causing the tools to change the design's logic; thus, the optimization stage is then removing logic based on this altered design. This is reflected in the timing simulation.
A simple fix is to change the design name so that it does not contain the keyword (e.g., "Nbay").
This problem is fixed in the latest 3.1i Service Pack, available at:
The first service pack containing the fix is 3.1i Service Pack 8.
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