The ECS schematic tool has a VHDL/Verilog netlist output; therefore, you must create a black box for this netlist as follows:
1. Open the EDIF file and find the port declarations for the top-level component (you will be entering these port names into a VHDL file).
(port a0 (direction INPUT))
. . .
2. Create a VHDL file using the entity and port names in the EDIF file, and leave the architecture statement empty.
entity rom2x1 is
Port (a0 : in std_logic;
d0 : out std_logic);
architecture behavioral of rom2x1 is
3. Add the VHDL file to the project as a VHDL module.
4. Highlight that VHDL file, and then select Design Entity Utilities -> Create Schematic Symbol.
5. Use this symbol in your schematic. When you implement your design, make sure that the netlist is in the same project directory, and NGDBuild will merge the external netlist with the top-level design.
Use the following steps to create a schematic symbol:
1. Use EDIF2NGD to create a "<filename>.ngo" file from the EDIF netlist. EDIF2NGD.exe converts an EDIF netlist (.edn, .edo, .edf, etc.) to an NGO file.
2. Use NGD2SPL to create a "<filename>.spl" file from the newly created "<filename>.ngo" file. NGD2SPL.exe parses the NGO file and creates an SPL file, which is a text file describing the inputs, outputs, bidirectional pins, and attributes for the symbol. NGD2SPL also adds a BOX_TYPE=BLACK_BOX attribute so that XST treats this symbol as a black box.
3. Use SPL2SYM to create a "<filename>.sym" file from the newly created "<filename>.spl" file. SPL2SYM.exe reads an SPL file and creates the ECS symbol file (SYM).
You can download a batch file that runs all three programs in one step from:
If the Project Navigator simulation language is set to Verilog, an additional module declaration file must also be created and added to the project.
4. Run Sym2Verilog to create a "<filename>.v" file from the newly created "<filename>.sym" file.
Sym2Verilog.exe should be given the base name of the symbol (.sym) file as the first argument. Sym2Verilog reads the ".sym" file and creates a Verilog file containing the module instantiation.
The "<filename>.v" file should be added to the Project Navigator project using the Project -> Add Source menu selection.
NOTE 1: This method has been tested on EDIF files created by Aldec, BLIF2Net, CORE Generator, Exemplar, OrCAD, and Viewlogic. You cannot use this method to create symbols from EDIF netlists created by NGD2EDIF because EDIF2NGD does not accept these files.
NOTE 2: Top-level EDIF files might not work in this flow. Although the flow described above will successfully create a schematic symbol for a top-level netlist, if the netlist contains I/O buffers (IBUF, OBUF, etc.) and I/O pads (IPAD, OPAD, etc.) instead of port definitions, implementation will fail during NGDBuild. For this flow to implement successfully, the EDIF netlist must be edited to include Port statements in the interface section of the top-level CELL.
NOTE 3: EDIF files created from BLIF2Net (sub-program of ABL2EDIF) in Foundation 3.3i and earlier versions contain encrypted cell names that cannot be interpreted by the current version of NGDBuild. See (Xilinx Answer 13507) for details.
NOTE 4: Step 1, EDIF2NGD, can be skipped if you already have an existing ".ngo" or ".ngc" file.
NOTE 5: Symbol bus pins should have indexes surrounded with parentheses. If the buses in the netlist use angle or square brackets, the symbol should be edited and bus names converted to use parentheses (e.g., 'Q(3:0)').
1. Create a symbol using File -> New -> Symbol.
2. In the Symbol Edit window, add the applicable pins (Add -> Pin). Make sure that the added pin names match the port names of the EDIF file.
3. Right-click the symbol sheet and select Object Properties.
4. In the Symbol Properties window, select New.
5. In the New Attribute window, type "black_box" in both the Attribute Name and Attribute Value fields. (Leave the Attribute Value Type as a String.) Click OK.
6. Select the newly added black box attribute in the Symbol Properties window and click Edit Traits.
7. Select Verilog or VHDL (whichever intermediate HDL the ISE project is set to; select both if you are unsure) and check the "Write this attribute:" option.
8. Finish the symbol with graphics and text, as appropriate. Save and Close the symbol sheet.
9. Add the newly created symbol to a schematic sheet and connect as appropriate.
NOTE: If Verilog is used as the intermediate HDL language (to check this, right-click on Design Utilities -> View HDL Functional Model and select Properties), the module ports will have to be declared. This can be done by creating a Verilog file with the same base name as the module and placing it in the project directory. The wrapper file simply contains a module declaration including the port names.
Example: File named tenths.v
module tenths (AINIT, CE, CLK, Q, Q_THRESH0);
output [3:0] Q;