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AR# 11148

4.1i CORE Generator - Asynchronous FIFO: The CORE Generator Viewer reports incorrect utilization numbers

Description

Keywords: Spartan-II, CORE Generator, COREGen, FIFO, viewer, LUT, register

Urgency: Standard

General Description:
In a Spartan-II, for an 8-bit-wide and 32-bit-deep Block RAM ( D_IP2a) Asynchronous FIFO, the CORE Generator Viewer reports:

1 block memory.
114 primitives (99% unplaced)
40 LUT
39 registers

MAP reports:

Number of Slices: 30 out of 192...15%
Number of Slices containing unrelated logic: 0 out of 30...0%
Number of Slice Flip Flops: 37 out of 384...9%
Total Number 4 input LUTs: 26 out of 384...6%
Number used as LUTs: 24
Number used as a route-thru: 2
Number of bonded IOBs: 21 out of 60...35%
Number of Block RAMs: 1 out of 4...25%
Number of GCLKs: 2 out of 4...50%
Number of GCLKIOBs: 2 out of 4...50%

Solution

Asynchronous FIFO and many other cores are built from other lower-level core modules, such as block memory, counters, and registers. When instantiating lower-level cores, the Asynchronous FIFO does not use all of the ports and resources present on the lower-level core.

When MAP is run, the logic from the lower-level core that is not connected and used will be trimmed. This can cause the actual utilization of the Asynchronous FIFO to be significantly lower than the pre-MAP estimates that are reported by the CORE Generator Viewer.
AR# 11148
Date Created 03/06/2001
Last Updated 09/11/2003
Status Archive
Type General Article