Number of Slices: 30 out of 192...15% Number of Slices containing unrelated logic: 0 out of 30...0% Number of Slice Flip Flops: 37 out of 384...9% Total Number 4 input LUTs: 26 out of 384...6% Number used as LUTs: 24 Number used as a route-thru: 2 Number of bonded IOBs: 21 out of 60...35% Number of Block RAMs: 1 out of 4...25% Number of GCLKs: 2 out of 4...50% Number of GCLKIOBs: 2 out of 4...50%
Asynchronous FIFO and many other cores are built from other lower-level core modules, such as block memory, counters, and registers. When instantiating lower-level cores, the Asynchronous FIFO does not use all of the ports and resources present on the lower-level core.
When MAP is run, the logic from the lower-level core that is not connected and used will be trimmed. This can cause the actual utilization of the Asynchronous FIFO to be significantly lower than the pre-MAP estimates that are reported by the CORE Generator Viewer.