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AR# 11171

3.3i SimPrim - "Setup violation on CLKA with respect to CLKB" message seen on block RAM timing simulations. (VHDL)


Keywords: simulation, timing, block RAM, RAMB4, CLKA, CLKB, setup, VHDL, 3.1i, 3.2i

Urgency: Standard

General Description:
During timing simulation, the following message is reported:

"Warning: Setup violation on CLKA with respect to CLKB at time 12345ps"

However, this warning does not seem to make sense, as no violation is seen in the simulator.


The warning above should be flagged only when the same address location is being accessed on both ports AND there is a setup time violation on one of the clock ports.

A known issue in the current simulation model is that it does not check for the conditions correctly; thus, it sometimes flags this warning message incorrectly.

This issue is fixed in the 4.1i software release.
AR# 11171
Date 11/13/2002
Status Archive
Type ??????