General Description: Running Verilog behavioral simulation of CORE Generator cores can take a significant amount of time. This may be due to the inefficient coding style of the C_REG_FD_V3_0.v model in Verilog. The C_REG_FD_V3_0 core is used by many other cores, such as the Multiplier and Block Memories cores.
In the current C_REG_FD_V3_0.v model, a large for-loop with several call functions is executed on every clock edge. This can cause the run-time to extend.
This problem has been fixed in Base Blox v6_0, which will be delivered in 4.1i IP Update #2.
Meanwhile, if you wish to speed up the simulation run-time, you can modify the C_REG_FD_V3.v (which is located in the /Xilinx/verilog/src/XilinxCoreLib directory) by replacing the code in Example 1 below with the code in Example 2. In Example 2, there is no loop, as there was in Example 1.
always@(posedge intCLK or intCE or intACLR or intASET or intAINIT) begin datatmp = data;