AR# 11207

4.1i CORE Generator - Running Verilog behavioral simulation can take long time due to inefficient coding styles adopted in core C_REG_FD_V3_0.v

Description

Keywords: CORE Generator, COREGen, C_REG_FD_V3_0.v, ModelSim , FDReg, simulation, long, time

Urgency: Standard

General Description:
Running Verilog behavioral simulation of CORE Generator cores can take a significant amount of time. This may be due to the inefficient coding style of the C_REG_FD_V3_0.v model in Verilog. The C_REG_FD_V3_0 core is used by many other cores, such as the Multiplier and Block Memories cores.

In the current C_REG_FD_V3_0.v model, a large for-loop with several call functions is executed on every clock edge. This can cause the run-time to extend.

Solution

This problem has been fixed in Base Blox v6_0, which will be delivered in 4.1i IP Update #2.

Meanwhile, if you wish to speed up the simulation run-time, you can modify the C_REG_FD_V3.v (which is located in the /Xilinx/verilog/src/XilinxCoreLib directory) by replacing the code in Example 1 below with the code in Example 2. In Example 2, there is no loop, as there was in Example 1.

Example 1:

always@(posedge intCLK or intCE or intACLR or
intASET or
intAINIT)
begin
datatmp = data;

for(i = 0; i < C_WIDTH; i = i + 1)
begin
if(intACLR === 1'b1)
datatmp[i] = 1'b0;
else if(intACLR === 1'b0 && intASET === 1'b1)
datatmp[i] = 1'b1;
else if(intAINIT === 1'b1)
datatmp[i] = AIV[i];
else if(intACLR === 1'bx && intASET !== 1'b0)
datatmp[i] = 1'bx;
else if(intACLR != lastintACLR &&
lastintASET != intASET &&
lastintACLR === 1'b1 &&
lastintASET === 1'b1 &&
intACLR === 1'b0 &&
intASET === 1'b0)
datatmp[i] = 1'bx;
else
begin
...


Example 2:

always@(posedge intCLK or intCE or intACLR or
intASET or
intAINIT)
begin
datatmp = data;
if(intACLR === 1'b1)
datatmp = 'b0; // 0-extends to all bits
else if(intACLR === 1'b0 && intASET === 1'b1)
datatmp = {C_WIDTH{1'b1}}; // explicit sizing
else if(intAINIT === 1'b1)
datatmp = AIV;
else if(intACLR === 1'bx && intASET !== 1'b0)
datatmp = 'bx; // X-extends to all bits
else if(intACLR != lastintACLR &&
lastintASET != intASET &&
lastintACLR === 1'b1 &&
lastintASET === 1'b1 &&
intACLR === 1'b0 &&
intASET === 1'b0)
datatmp = 'bx; // X-extends to all bits
else
begin
...
AR# 11207
Date 09/11/2003
Status Archive
Type General Article