AR# 11231

Precision Synthesis - How do I retain hierarchy in Precision?

Description

Keywords: Precision, Synthesis, HDL, VHDL, Verilog, directive, constraint

Urgency: Standard

General Description:
How do I retain hierarchy in both my synthesis flow and implementation flow?

Solution

You can retain hierarchy in the synthesis flow by passing the "hierarchy" directive through the HDL code:

VHDL
:
attribute hierarchy : string;
attribute hierarchy of comp_inst : label is "preserve";
:
:

Verilog
//pragma attribute comp_inst hierarchy "preserve";

Precision currently does not support the passing of the KEEP_HIERARCHY implementation constraint. This constraint can be passed by the UCF.

For more information on the KEEP_HIERARCHY UCF constraint, please refer to the Constraints Guide:
http://support.xilinx.com/support/software_manuals.htm
AR# 11231
Date 04/20/2007
Status Archive
Type General Article