UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
Page Bookmarked
  1. Xilinx - All Programmable
  2. Support
  3. AR# 11288: 3.1i CORE Generator - Verilog :8b/10b decoder: Error does not detect 1000000111 even though there are six zeros in a row

AR# 11288

3.1i CORE Generator - Verilog :8b/10b decoder: Error does not detect 1000000111 even though there are six zeros in a row

Description

Keywords: CORE Generator, COREGen, 8b, 10b, Decoder, error, 1000000111, Code_err, does, not, high, six, zeros, Verilog

Urgency: Standard

General Description:
In the 8b/10b Decoder core, an error should occur when five or more zeros occur in succession, and code_err should go high. However, when the input is at 1000000111, this does not happen.

Solution

This issue has been fixed in Version 2_0 of 8b/10b Decoder, which is available in IP_Update#3 (D_IP3) and newer IP updates.

For the latest IP updates, go to the Xilinx IP center at:
http://www.xilinx.com/ipcenter/coregen/updates.htm
AR# 11288
Date 08/23/2002
Status Archive
Type General Article