When I create a schematic symbol from a VHDL source in Project Manager, the following error occurs ("main" is the VHDL and entity name, and "FD" is a component instantiated in "main"):
This problem occurs when the component is not created completely in VHDL-87 syntax or completely in VHDL-93 syntax.
In the VHDL-93 example below, the "is" at the end of the first line and the component name (FD) at the end of the last line are optional.
However, if one but not the other is used, the "Create Schematic Symbol" process reports the error:
This is a problem with the VHDL analysis in the "Create Schematic Symbol" process only.
It does not affect standard VHDL synthesis.
Either include both the "is" at the end of the first line and the component name at the end of the last line, or omit both when you create schematic symbols from a VHDL source.