4.1i Virtex-II PAR - Placer rejects valid BUFGMUX configurations.
Keywords: place, BUFGMUX, 3.1i
General Description: The Virtex-II placer rejects pairs of primary/secondary BUFGMUX LOC constraints based on a faulty DRC check. This check reports that the two BUFGMUX's drive loads that are in the same quadrant, which is not supported by the hardware. Placement fails with the following message:
ERROR: Place - The global clocks clocks.tclk_2x_90_bufg and clocks.ib_iclk2_bufg are locked into a primary / secondary site pair. It is impossible to route all of the inputs to both of these clocks using the global clock combs. Remember that only one of these clocks may have access to any one quadrant so if these two clocks drive multiple loads on a single-component or drive inputs to multiple components locked into the same quadrant, the nets will not be routable using the clock comb. Please correct this before continuing.
Most occurrences of this problem are resolved by a fix in the 4.1i release; however there are also issues that will be fixed in the first 4.1i service pack.
In 3.1i or 4.1i, the faulty check can be bypassed by setting the following environment variable:
SET XIL_PAR_SKIPAUTOCLOCKPLACEMENT=1 (PCs) setenv XIL_PAR_SKIPAUTOCLOCKPLACEMENT 1 (Workstations)
When using this environment variable work-around, all clock components must be LOC'd.
Also, 4.1i Service Pack 2 contains a messaging enhancement so that when this error occurs for valid cases, specific information about the affected BUFGMUXs will be printed. This will include a list of load components by quadrant. You may also contact the Xilinx hotline (1-800-255-7778) for assistance in debugging BUFGMUX configurations with this error.