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AR# 11417

4.1i SIMPRIMS, NGD2VHDL, NGD2VER - Performing post-Place and Route simulation without using the SDF file. (VHDL, Verilog)


Keywords: NGD2VHDL, NGD2VER, NGDAnno, SimPrim, SDF, simulation, support, VHDL, Verilog, timing

Urgency: Standard

General Description:
Is back-annotated (timing) simulation after Place and Route supported if the SDF file is not used?


For post-MAP and post-PAR simulations, NGDAnno creates an SDF file to annotate the delay information. Since the SimPrim models are designed to account for these delays, removing the SDF file can cause race conditions or other undesired results.

Therefore, at this time, the SDF file should always be used for post-MAP and post-PAR simulations.
AR# 11417
Date 05/05/2004
Status Archive
Type General Article