If I am not using the dedicated JTAG pins on a Xilinx device, what should I do with them?
Can I leave them floating?
Should they be tied High or Low?
Do the JTAG pins on Xilinx devices need external pull-up resistors?
For more FPGA Device Specific Issues and other Configuration Related Articles, see (Xilinx Answer 34104).
This Answer Record applies to all Xilinx devices.
Xilinx recommends that you always bring out your JTAG signals for potential use at a later time.
These pins can be very helpful when you debug or reconfigure your device.
If you are not using JTAG on your device, Xilinx recommends that you tie both TDI and TMS to VCC through a small resistor (i.e., 4.7k).
Although Virtex JTAG ports have internal pull-ups that are connected by default on TDI and TMS, Xilinx suggests using the external pull-ups to ensure that the device does not enter Boundary Scan mode.
It is not necessary to place a pull-up resistor on TCK or on the output TDO; they can be left floating.
Although not required, it is a good idea to bring out all four JTAG pins so that you can access them if necessary.