AR# 11457: 3.1i Virtex-II MAP - ORCY circuit leads to fatal error during related packing.
3.1i Virtex-II MAP - ORCY circuit leads to fatal error during related packing.
Keywords: basncsignal, 249, Could not find a bel, BY, bel, ORCY, related
General Description: A Virtex-II circuit containing an ORCY symbol fails in MAP with the following error:
FATAL_ERROR:Ncd:basncsignal.c:249:18.104.22.168 - Could not find a bel for a signal on pin BY of comp qa_eq_b. Its current programmed state is : CYSELF:F CYSELG:G YUSED:0 CYINIT:CIN DYMUX:1 F:#LUT:D=((~A1*((A2@~A4)*~A3))+(A1*((A2@~A4)*A3))) SYNC_ATTR:SYNC SRFFMUX:0 FFY_SR_ATTR:SRLOW FFY:#FF CY0G:0 GYMUX:SOPEXT CY0F:0 FFY_INIT_ATTR:INIT0 G:#LUT:D=((~A1*((A2@~A4)*~A3))+(A1*((A2@~A4)*A3))) BYINV:BY CEINV:CE CLKINV:CLK SRINV:SR SOPEXTSEL:0 Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com
NOTE: This Answer Record only addresses your issue if all of the following statements are true:
1. The architecture is Virtex-II. 2. The error message mentions the "BY" pin. 3. The circuit involves an ORCY symbol.
This problem has been fixed in the 4.1i release, which is currently scheduled for release in August, 2001.
Meanwhile, you can work around this problem by overriding the RLOC constraint on the register that is driven by the OR. The following UCF entry illustrates the way to do this:
INST "F1" USE_RLOC = FALSE ;
The drawback of this work-around is that the register does not get packed into the same slice with the ORCY.