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AR# 11510

FPGA I/O - Can differential inputs, such as LVDS or LVPECL, be left undriven?


What are the consequences of leaving a differential input undriven? Should I DC-bias the inputs? Is there any risk of damage to the device?


If the logical state of the differential receiver'spins is not important when they left un-driven (e.g., if input registers have been disabled), you do not need to do anything. The receiver's output might toggle if enough noise is present; however, this will not damage the device. The toggling might lead to increased power consumption and noise within the device; however, these will be fairly insignificant.

If it is necessary to keep the receiver'spins at a known logical state, the inputs can be DC-biased with a pull-up to 2.5V and pull-down to GND, each 2490 ohms (standard 1% value resistor). Assuming the pull-up is attached to the p-side and the pull-down to the n-side, this will result in a logical "1" at the receiver pins. This scheme provides the best compromise for noise immunity and duty-cycle distortion.
AR# 11510
Date 03/03/2013
Status Active
Type General Article