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AR# 11510

FPGA I/O - Can differential inputs, such as LVDS or LVPECL, be left undriven?


What are the consequences of leaving a differential input un-driven? Should I DC-bias the inputs? Is there any risk of damage to the device?


If the logical state of the differential receiver's pins is not important when they left are un-driven (for example, if input registers have been disabled), you do not need to do anything. 

The receiver's output might toggle if enough noise is present; however, this will not damage the device. The toggling might lead to increased power consumption and noise within the device; however, these will be fairly insignificant.

If it is necessary to keep the receiver's pins at a known logical state. The inputs can be DC-biased with a pull-up to VCCO and pull-down to GND.

The design goal is to get the input differential voltage to a level that ensures a known logic level is at the IBUFDS output, while still ensuring that the signal integrity is good at the input pin.

You should select the Pull-up and Pull-down resistors such that in the undriven case the differential input voltage is greater than the minimum VID for the differential input standard in the data sheet.

Then perform an IBIS or Spice simulation with the input being driven at the desired operating frequency to ensure that the input specifications are still met and that there is good signal integrity at the input.

Linked Answer Records

Master Answer Records

Answer Number Answer Title Version Found Version Resolved
47900 SelectIO Design Assistant: Interfacing to Xilinx devices N/A N/A
AR# 11510
Date 04/04/2017
Status Active
Type General Article
  • FPGA Device Families