UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!
  1. Xilinx - Adaptive. Intelligent.
  2. Support
  3. AR# 11531: 3.1i Virtex-II Speed Files - Incorrect delay on differential buffers

AR# 11531

3.1i Virtex-II Speed Files - Incorrect delay on differential buffers

Description

Keywords: time_sim, edn, LVDS, IBUFDS

Urgency: Standard

General Description:
The speed files for the Virtex-II are not reporting symmetrical delays for both pairs of differential input pins. (This information is reported in the time_sim file.)

An instance of this behavior is illustrated in the following snippet from a time_sim.edn. (Note that "portInstance IB" has no values.):

(instance (rename &_I10 "$I10")
viewRef view_1 (cellRef x_ibufds (libraryRef SIMPRIMS)))
(portInstance O
property RISE (integer 697)(unit TIME) (owner "Xilinx"))
(property FALL (integer 697)(unit TIME) (owner "Xilinx")))
(portInstance IB)
(portInstance I
(property RISE (integer 685)(unit TIME) (owner "Xilinx"))
(property FALL (integer 685)(unit TIME) (owner "Xilinx"))))

Solution

This problem is fixed in the latest 3.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates.
The first service pack containing the fix is 3.1i Service Pack 8.
AR# 11531
Date 08/26/2002
Status Archive
Type General Article

By using this website, I accept the use of cookies.   Learn more

Page Bookmarked