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AR# 11532

3.1i Virtex-II Speed Files - Improved delay modeling for the Virtex-II registered multiplier

Description

Keywords: MULT18X18S, MULT18X18, synchronous

Urgency: Standard

General Description:
The Virtex-II registered multiplier (MULT18X18S) has only a single setup delay; however, the setup delay actually varies according to which pin is used to feed the multiplier.

The model was updated by the addition of distinct setup delays for different input pins.

Solution

This problem is fixed in the latest 3.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates.
The first service pack containing the fix is 3.1i Service Pack 8.

NOTE: This fix affects ONLY the delay annotation of the MULT18X18S component. To access MULT18X18S in 3.1i software, you need to manually enable it in FPGA Editor.

This is fixed in the 4.1i release, where the MULT18X18S instantiated in EDIF is automatically implemented.
AR# 11532
Date Created 05/03/2001
Last Updated 08/26/2002
Status Archive
Type General Article