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AR# 11543

3.1i XST - XST inserting a BUF after a BUFGMUX.

Description

Keywords: XST, BUFGMUX, BUF, slice, Virtex-II, extra

Urgency: Standard

General Description:
When running a Virtex-II design through XST using a BUFGMUX for Virtex-II, XST inserts an extra BUF in the path. This causes extra delay in the path.

NOTE: This problem is fixed in the 4.1i release.

Solution

1

VHDL Solution:

library ieee;
use ieee.std_logic_1164.all;

entity bufgmux_ff is
port (d : in std_logic;
clk : in std_logic;
q : out std_logic);
end entity;

architecture bufgmux_ff_arch of bufgmux_ff is

attribute max_fanout : string;
attribute max_fanout of clk_int : signal is "100000";

attribute keep : string;
attribute keep of clk_int : signal is "true";

component bufgmux is
port (i0 : in std_logic;
i1 : in std_logic;
s : in std_logic;
o : out std_logic);
end component;

signal ground, clk_int : std_logic;

begin

ground <= '0';

bufg_mux_inst : bufgmux port map (clk, ground, ground, clk_int);

process (clk_int) begin
if clk_int'event and clk_int = '1' then
q<=d;
end if;
end process;

end architecture;

2

Verilog Solution:

module bufgmux_ff (d, clk, q);

input d, clk;
output q;

wire ground, clk_int;
//synthesis attribute keep of clk_int is "true"
//synthesis attribute max_fanout of clk_int is "100000"

reg q;

assign ground = 1'b0;

BUFGMUX gufgmux_inst (.I0(clk), .I1(ground), .S(ground), .O(clk_int));

always@(posedge clk_int) q<=d;

endmodule
AR# 11543
Date Created 05/07/2001
Last Updated 08/19/2002
Status Archive
Type General Article