We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 11560

LogiCORE SPI-4.2 (POS-PHY L4) v3.x - Verilog simulation does not work: Data on the RDat bus is presented out of order in a Sink FIFO


General Description:

When I run timing simulation with the Xilinx POS-PHY L4 core, the simulation does not work because of a race condition created by the back-annotated model.

No error is given by the simulator, but the outputs of the PL4's Sink side logic are incorrect. The typical symptom is a re-ordering of the data (byte pairs are swapped) at the Sink FIFO's output.

This problem is simulator-dependent. (The Verilog-XL is one of the simulators that has this problem.)


This problem has been fixed as of the 4.1i software. All subsequent software releases also contain this fix.

Current ISE software is available at:


To work around this problem, modify your x_inv.v file, which is located in <XILINX>\verilog\src\simprims (where <XILINX> is your Xilinx installation directory).

Change the following line from:

specparam ODLYLH = 100:100:100, ODLYHL = 100:100:100;


specparam ODLYLH = 10:10:10, ODLYHL = 10:10:10;

AR# 11560
Date 05/03/2010
Status Archive
Type General Article