AR# 11614

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3.x FPGA Express - FPGA Express does not synthesize comparators correctly

Description

Keywords: FE, FPGA Express

Urgency: Standard

General Description:
FPGA Express synthesizes the following comparator incorrectly:

DOUT <= '1' when (DIN_A) > (DIN_B & "111111111111111111") else '0';

(If the bit width is narrow, this should not be a problem.)

Solution

Please compare upper bits.

If you are using Virtex, Virtex-E, or Spartan-II, you may use the comparator that is available in CORE Generator.
AR# 11614
Date 08/11/2003
Status Archive
Type General Article
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