AR# 11618: 3.1i, Virtex-E speed file - Virtex-E Speed File updates in Service Pack 8
3.1i, Virtex-E speed file - Virtex-E Speed File updates in Service Pack 8
Keywords: Virtex-E, speed file, service pack
General Description: What updates have been made to the Virtex-E speed files in 3.1i Service Pack 8?
As part of our normal effort to more accurately model the performance of the Virtex-E family of devices, we have re-assessed various delay parameters of the Virtex-E speed file. The performance engineering team extensively analyzed characterization data, production test results, and reported field performance, and indicated that a few delays need to be revised.
The first change involves the horizontal HEX line delays on the edge of the chip. All horizontal edge HEX line delays have been increased by 300 psec, regardless of speed grade.
Second, the Tbcko (for the fastest speed grade only) has increased from 1.09ns. to 2.45ns.
Finally, as part of our normal process to ensure that the speed file reflects actual silicon performance, there have been minor adjustments (both faster and slower) to other delays.
Actions that should be taken
Current designs should be at least re-timed with the new speeds files. This will flag any potential problems. If no new timing errors result, then the design is not impacted by these changes. Any new timing errors can be corrected by simply re-running the design through Place and Route with the new speed files.