AR# 11653: 3.x FPGA Express - How do I prevent global buffer insertion (keep BUFGs from being inferred)?
3.x FPGA Express - How do I prevent global buffer insertion (keep BUFGs from being inferred)?
Keywords: prevent, global buffer, insert, insertion, BUFG
General Description: How do I prevent global buffer insertion (i.e., How do I keep BUFGs from being inferred)?
There are two ways to accomplish this. (The first is the preferred method.)
1. Open FPGA Express in stand-alone mode.
For example, on a Windows machine:
Start -> Programs -> Xilinx Foundation Series -> Accessories -> FPGA Express
2. Create a project and synthesize your design.
3. Highlight a file in the "Chips" window.
4. Open the tool's Constraints Editor by going to Synthesis -> Edit constraints
5. Go to the PORTS tab.
6. In the "Global Buffer" column, select "DONT USE" next to all the clock nets that should avoid BUFGs.
7. If you would like all clock nets to avoid BUFGs in the future, make the following change before closing the Constraints Editor:
- In the "Global Buffer" column, select "DONT USE" next to the net labeled "<default>".
Method 2 (For users who do not have access to the Constraints Editor)
This less refined method does not require the Constraints Editor; rather, it uses the command line version of FPGA Express.
1. Open FPGA Express in stand-alone mode, and export a script after having optimized and exported a netlist.
(From within FPGA Express, go to Script -> Export Script.)
2. Insert this line
set_pad_buffer "DONT USE" <clock name>
just before the optimize_chip command (see example below).
3. Run the script in the fe_shell. (It is located in %XILINX%\synth\bin-win32i -- this is the FPGA Express command line shell.) It is very similar to UNIX, so simply "cd" to the script directory and run "source script.fes".