General Description: When I compile my XilinxCoreLib simulation libraries using the xilinx_lib.tcl script from (Xilinx Solution 8066), many of the models do not get compiled.
Solution
This problem is caused by an incomplete vhdl_analyze_order file; this file is kept in the $Xilinx/vhdl/src/XilinxCoreLib directory written by Service Pack 8.