We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Page Bookmarked

AR# 11722

Virtex/-E/-II/-II-Pro/-4/-5/-6, Spartan-3/-3E/-3E/-3A - Why must all "VREF" connections in a given bank be tied to the same power source?


Data sheets for FPGA familes note that voltage reference (VREF) inputs must come from the same external source. Why is this the case?


The "VREF" inputs are high-impedance nodes and are very susceptible to coupling. For correct system operation, it is very important to maintain a reliable voltage level on these inputs. Connecting them to the same source provides for lower impedance and reduces this risk.

Also, Xilinx recommends that the "VREF" inputs are decoupled externally. For more information on proper decoupling for Virtex devices, please see the Xilinx Application Note (Xilinx XAPP623): "Power Distribution System (PDS) Design: Using Bypass/Decoupling Capacitors."

AR# 11722
Date 12/15/2012
Status Active
Type General Article