AR# 11726


Xilinx Application Note 209 - A number of CRC and data-width options do not produce synthesizable code


Keywords: CRC, Application Note, AppNote, 209, code

Urgency: Standard

General Description:
Perl script produces synthesizable code only if the CRC width is larger than the data width AND is a multiple of the data width. In all other cases, the generated code is not synthesizable.

How do I make the code synthesizable?


This issue and related information is discussed in Xilinx Application Note 209: "IEEE 802.3 Cyclic Redundancy Check v1.0" (Xilinx XAPP 209).

This known issue was fixed in July, 2001.

It is also possible to make the following modifications to the generated code:


Change Line 35 from

output [31:0] crc_reg;


output [7:0] crc_reg; //changed from 31:0


Change Line 45 from

reg [31:0] crc_reg;


reg [7:0] crc_reg; //changed from 31:0


Change Lines 90 - 93 from

else if (~calc & d_valid) begin
crc_reg <= {crc_reg[-1:0], 8'h00};
crc <= ~{crc_reg[-8], crc_reg[-7], crc_reg[-6], crc_reg[-5],
crc_reg[-4], crc_reg[-3], crc_reg[-2], crc_reg[-1]};


else if (~calc & d_valid) begin //crc_reg [] and crc changed
crc_reg <= 8'h00;
crc <= ~{crc_reg[7], crc_reg[6], crc_reg[5], crc_reg[4],
crc_reg[3], crc_reg[2], crc_reg[1], crc_reg[0]};

AR# 11726
Date 10/01/2008
Status Archive
Type General Article
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