AR# 11754


Virtex-II, Virtex-II Pro, Virtex-4, Virtex-5 I/O Modeling (IBIS, SPICE) - How should package parasitics be modeled?


The switching speed of all Virtex family devices starting with Virtex-II requires a new approach for package modeling. 

This includes Virtex-II, Virtex-II Pro, Virtex-4, and Virtex-5. 

This Answer Record describes the approach recommended by Xilinx.


There are two primary package types to consider: wirebond (BG*, FG*) and flip-chip (FF*, BF*).

The IBIS specification provides a method for specifying a lumped set of resistance, capacitance, and inductance parameters for any given package.

These values are set in an IBIS model using the R_pkg, C_pkg, and L_pkg identifiers. 

When a package functions as a transmission line (as it does when rising/falling edges are very short in duration), this approach is not accurate.

Laboratory measurements have shown that the bond wires (BG*, FG*) and redistribution layer (BF*, FF*) exhibit very similar RLC characteristics.

As a result, there is a single set of RLC numbers in the Virtex IBIS file that applies to all package types.

These numbers should not be changed.

Both package types also contain the signal trace, which must be modeled as a transmission line.

Laboratory measurements have shown that the trace can best be modeled as a 50-65 ohm transmission line with variable delay.

In the BG* and FG* packages, the delay is 10-100 ps.

In the BF* and FF* packages, the delay is 10-200 ps.

Pin-specific delays can be found in the PACE software tool (part of the ISE design suite).

IBIS models for all Xilinx devices are available at:

Note: This Answer Record does not apply to the RocketIO Multi-Gigabit Transceivers (MGTs).

The MGTs must be simulated using HSPICE models for both the buffers and the package.

These models are available for download in:

AR# 11754
Date 04/06/2018
Status Active
Type General Article
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