We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 11773

LogiCORE Viterbi Decoder v1.0 - Core Generator 3.1i Viterbi Decoder core fails to generate for large constraint lengths


Keywords: FEC, decoder, forward error correction

For large Viterbi cores constraint length 9, Core Generator may fail and not generate the core do to memory issues.


For large Viterbi cores constraint length 9 the mx command needs to be increased from the current setting of 1024 to 2047

e.g. $JAVA_HOME/bin/jre" -mx2047m -ss4M -DLDLIBPATH="$LD_LIBRARY_PATH" -classpath "$CLASSPATH" com.xilinx.encore.coregen.main.Coregen -c $COREGEN -p /home/beth/CoregenRun -b large.xco or refer to (Xilinx Solution 9244) for more information on changing the coregen.bat file.

Please See (Xilinx Answer 29448) for a detailed list of LogiCORE Viterbi Decoder Release Notes and Known Issues.
AR# 11773
Date 03/14/2008
Status Archive
Type General Article