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AR# 11799

4.1i NGD2VHDL, SIMPRIMS - Can the back-annotated netlist (time_sim.vhd) be compiled with the VHDL '93 syntax? (VHDL)

Description

Keywords: Modelsim, time_sim.vhd, vhd93, vhdl, timing, simulation

Urgency: Standard

Description:
Can the back-annotated netlist (time_sim.vhd) be compiled with the VHDL '93 syntax?

Solution

The back-annotated netlist generated by the Xilinx ISE 4 tools are written in the
VHDL 87 syntax. Therefore, they cannot be compiled using the VHDL '93 syntax.

The back-annotated design can still be used alongwith other files that are written
in the VHDL '93 syntax. For compilation purposes, use the "-87" switch in Modelsim
for compiling the back-annotated netlist, and use the "-93" switch for files written
in the VHDL '93 syntax.
AR# 11799
Date Created 08/29/2007
Last Updated 08/15/2003
Status Archive
Type ??????