AR# 11856


Virtex/E - Readback timing information (XAPP 138)



The Virtex data sheet and Xilinx Application Note "Virtex FPGA Series Configuration and Readback" (Xilinx XAPP 138) do not specify timing information for readback. What are the CS to high-Z and clock-to-out times for readback?


While this information has not been fully characterized, conservative figures are available: 


1. CS -> high-Z: 30ns 


The CS->high-Z parameter gives the amount of time from the de-assertion of CS to high-Z on the D[0:7] pins. 


2. Clock-out: 25ns 


Clock-out is the time from a rising clock edge to valid data presented on the D[0:7] pins.

AR# 11856
Date 05/08/2014
Status Archive
Type General Article
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