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  3. AR# 1186: XNF2WIR ERROR 217: The logical function of <component> and its Viewlogic model do not match.
  4. AR# 11863: Signal Integrity and the PCB - How do I determine the transition times of FPGA outputs?

AR# 11863

Signal Integrity and the PCB - How do I determine the transition times of FPGA outputs?

Description

General Description:

How do I determine the transition times of FPGA outputs? Does Xilinx specify these parameters?

Solution

Given the speed at which today's advanced semiconductors switch, PCB traces as small as one inch appear as transmission lines. Signal behavior can thus be influenced by transmission line effects such as crosstalk and ringing.

Signal behavior is also affected by variations in process, temperature, and power supply. Because of these dependencies, Xilinx is unable to specify output transition times in a general manner. The best way to determine how a switching output will behave is to perform an IBIS simulation.

IBIS models for Xilinx devices can be found at:

http://support.xilinx.com/support/sw_ibis.htm

For more information regarding Signal Integrity Engineering, visit "SI Central":

http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Signal+Integrity

AR# 11863
Date 02/07/2013
Status Active
Type General Article