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AR# 11869

4.1i CORE Generator - Synthesizing ISE design with Dual/Single-Port Block Memory caused "ERROR:Xst:1024 - memory_comps.vf Line 33. No port named 'CLKA'"

Description

Keywords: CORE, Generator, COREGen, Foundation, ISE, dual, single, port, block, memory, XST, synthesis

Urgency: Standard

General Description
When synthesizing a Virtex-II design using 4.1i Foundation ISE, I encounter the following error (I have CORE Generated Single- or Dual-Port Block Memory in my design):

ERROR:Xst:1024 - memory_comps.vf Line 33. No port named 'CLKA'
ERROR:Xst:1024 - memory_comps.vf Line 33. No port named 'ADDRB'
ERROR:Xst:1024 - memory_comps.vf Line 33. No port named 'DINB'
ERROR:Xst:1024 - memory_comps.vf Line 33. No port named 'WEB'
ERROR:Xst:1024 - memory_comps.vf Line 33. No port named 'CLKB'
ERROR:Xst:1024 - memory_comps.vf Line 33. No port named 'DOUTB'
==========
Line 33 from memory_comps.vf contains:
dual_port XLXI_1 (.ADDRA(), .DINA(), .WEA(), .CLKA(XLXN_12),
.ADDRB(XLXN_13[3:0]), .DINB(XLXN_14[15:0]), .WEB(XLXN_15),
.CLKB(XLXN_16), .DOUTA(), .DOUTB(XLXN_1[15:0]));

dual_port.v (which is synthesized) contains:
module dual_port (
addra,
addrb,
clka,
clkb,
dina,
dinb,
douta,
doutb,
wea,
web); // synthesis black_box

Solution

This problem occurs because CORE Generator writes out Single- or Dual-Port Block Memory Symbol ports in upper-case characters, and the Verilog instantiation file has ports that are written in lower-case letters.

To work around this problem, edit your Verilog design files, searching for all the Block Memory modules generated by CORE Generator, and change all the port names to upper-case characters.
AR# 11869
Date Created 06/27/2001
Last Updated 09/11/2003
Status Archive
Type General Article