AR# 11879


3.1i CORE Generator - When XilinxCoreLib is compiled with NC-VHDL, lfsr_v1_0.vhd reports "Error 21: Expecting a locally static expression of type integer."


Keywords: CORE Generator, COREGen, XilinxCoreLib, NC-VHDL, simulator, compilation, LFSR, D_IP4

Urgency: Standard

General Description:
When I compile XilinxCoreLib with NC-VHDL, the following error is reported on lfsr_v1_0.vhd:

"Error 21: Expecting a locally static expression of type integer."
(The declared integer is c_size.)



There is a problem in the lfsr_v1_0.vhd file that was not detected by MTI VHDL simulator. Currently, Xilinx only tests XilinxCoreLib with the MTI Simulator; therefore, some problems may be detected if other simulators are used.

This problem is scheduled to be fixed in an upcoming IP update. However, as the IP developers do not currently have access to NC-VHDL, we cannot guarantee which IP update will contain the fix.


If you are not using LFSR V1_0, (and do not intend to use it in the near future), you can remove lfsr_v1_0.vhd file from the VHDL analyze order, and no compilation errors will occur.

If you decide to use the LFSR v1_0 core, you should be able to generate and implement it. However, you will not be able to perform behavioral simulation on this core.

However, there is an option to perform post-NGDBuild simulation; please see (Xilinx Answer 8065) for more information.


If you would still like to be able to perform behavioral simulation on LFSR, follow this quick work-around:

1. Comment out lines 102-133 of lfsr_v1_0.vhd (the entire CASE statement from CASE to END CASE).

2. Replace this with the line: cur_state <= 0;

As this will completely break the functionality of the DATA_VALID and NEW_SEED outputs, the core must NOT be generated with either of these output ports present. This work-around will allow the code to compile by eliminating the problem CASE statement.
AR# 11879
Date 08/23/2002
Status Archive
Type General Article
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