AR# 11908


3.1i Project Navigator: Verilog flow uses file name instead of module name


Keywords : ISE, Project Navigator, verilog, module, file name

Urgency : Standard

General Description:

Adding source files or copies of source files to a project can cause the GUI to

get into a mode where it no longer looks inside the verilog file to determine the

module's name. It merely labels the module name the same as the source file name.

So, in the hierarchy window where files are shown where the form should be:

module_name (file_name.v)

appears the following:

file_name.v (file_name.v)

No amount of editing on the file, i.e. changing the module name, will

cure this. Subsequent files added are also added incorrectly, once the

software has entered this mode.

This causes the hierarchy to be incorrect and the files with their

erroneous module names cannot be processed.


A dummy file must be created from the Project Navigator and added to the


This dummy file must be created in this manner. Go to Project -> New

Source -> select file type = verilog module, and give it a name like

"bogus" and leave "Add to Project" checked. Hit Next and Next, which

adds this file. It will add the file incorrectly with the module name

equal to the file name. Now highlight the "bogus" file and use the

delete key to delete it. Magically, your other files will get there

module names updated correctly.

This issue has been resolved in the 4.1i release of the software.

AR# 11908
Date 01/06/2010
Status Archive
Type General Article
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