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AR# 11958

4.1i Project Navigator - Testbench port mismatch from source will generate errors during simulation


Keywords: port, std_logic, vector, downto, testbench, source

Urgency: Standard

General Description:
If a port is declared as "std_logic_vector (0 downto 0)" in a VHDL source file, the VHDL testbench generated by Project Navigator shows the port as "std_logic".

This will cause the following warning to be reported in ModelSim:

"# WARNING[1]: file.vhd(xx): Types do not match for port xxx."

The simulation will not start due to a type mismatch (binding) error.


If a testbench is to be generated by Project Navigator, "std_logic_vector (0 downto 0)" cannot be used in the source. The source port must be changed to "std_logic".

This issue has been fixed in the 5.1i release of the software.
AR# 11958
Date 08/11/2003
Status Archive
Type General Article