AR# 11960


5.1i PAR, Virtex-II - Placing RAM16X1S and RAM32X1S in the odd column causes "WARNING:Route:47 - The signal "ram/A4'" is not completely routed"


General Description: 

PAR reports the following warning whenever RAM16X1S or RAM32X1S is placed on an odd column: 


"WARNING:Route:47 - The signal "ram/A4'" is not completely routed." 


Why does this warning occur?


The address cannot be routed because of routing limitations. 


The following rules apply to placement of RAM16X1S and RAM32X1S in Virtex-II: 


- The hardware supports up to two independent 32x1 RAMs in a CLB. These must be placed in slices S0 and S1. Slices S2 and S3 are then unavailable for use as independent RAM. Those slices may contain LUTs or shift registers.  


- The hardware supports up to four independent 16x1 RAMs in a CLB. These must be placed in slices S0 and S1. For every F or G function generator used as a 16x1 RAM, the corresponding F or G in slices S2 and S3 are unavailable for use as independent RAM. These function generators may be used as a LUT or shift register.


VIrtex-II logic block information 


In Virtex-II devices, one configurable logic block (CLB) consists of four slices with specific routing resources. The placement of RAM16x1S and RAM32X1S in a Virtex-II CLB is affected by the shared routing resources of the write addresses in the CLB. 


Please see the following figure: 

Virtex-II CLB, 4 slices
Virtex-II CLB, 4 slices


The figure illustrates the way a Virtex-II CLB (4 slices) appears in FPGA Editor. The physical location in this example is SLICE_X6Y0, SLICE_X6Y1, SLICE_X7Y0, and SLICE_X7Y1, corresponding to S0, S1, S2, and S3, respectively. (The array starts in the bottom-left area of the chip as X0Y0, with increasing X# to the right and increasing Y# going upwards.) 


The slices are grouped into two columns:  

- S0 and S1 in X6 (even) column 

- S2 and S3 in X7 (odd) column 


The net highlighted in red is WF4 (a write address to the F LUT), which is shared by S0 and S2. S2's LUT write addresses are tied to the LUT inputs from S0. Similarly, S3's LUT write addresses come from S1; a RAM16X1S or RAM32X1S RAM in S2 must have the same write address as the RAM16X1S/RAM32x1S in S0. Because of this, if you put RAM32x1S RAMs in both S0 and S2, you cannot have two independent 32x1's -- instead, you should have a 32x2 or a 32x1DP.  


Therefore, a CLB can easily contain a 32x4 RAM. It cannot, however, contain 4 32x1 RAMs that do not share addresses.  


Note that the write addresses to S3 and S2 come from the LUT inputs on S1 and S0. Thus, the write addresses of S3 and S2 depend on the LUT input of S1 and S0, respectively.

AR# 11960
Date 05/14/2014
Status Archive
Type General Article
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