What is the difference between Cycle-Cycle Jitter and Period Jitter as they are discussed in the Virtex-II FPGA data sheet?
Period jitter and cycle-cycle jitter are two (of many) different ways of characterizing clock jitter. Both specifications describe statistical variation from a mean value.
Period jitter is the worst-case deviation from the average clock period of all clock cycles in the collection of clock periods sampled (which is usually 100,000 to 1M+ samples for specification purposes). In a histogram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period between adjacent clock cycles in the collection of clock periods sampled. In a histogram of cycle-cycle jitter, the mean value is zero.
For example, in low frequency mode, you specify tolerances of +/-300 ps of cycle-cycle jitter and +/-1.0 ns of period jitter. This means that for all times, your input clock period is allowed to vary by up to +/-1.0 ns. However, from any single clock period to the next, the variation is limited to +/-300 ps.
These two jitter characteristics affect the DCM in different ways, and the DCM is more tolerant of longer-term period changes than it is of shorter-term period changes.