Urgency: Hot
General Description;
When I run timing analysis on my design, I notice that a path ends with a net connecting to the clock pin, but there is no setup time or propagation delay associated with the destination component. How can I get this information?
This problem is fixed in the latest 4.1i Service Pack, available at:
http://support.xilinx.com/support/techsup/sw_updates
The first service pack containing the fix is 4.1i Service Pack 2.
| AR# 12021 | |
|---|---|
| Date | 01/18/2010 |
| Status | Archive |
| Type | General Article |