AR# 12051: HDL Bencher - Verilog ports that have the same name, but are written out different cases, produce errors when loaded in HDL Bencher.
AR# 12051
HDL Bencher - Verilog ports that have the same name, but are written out different cases, produce errors when loaded in HDL Bencher.
Description
Keywords: case, sensitive, port, Verilog
Urgency: Standard
General Description: If a Verilog module has a port named "DATA" and another port named "data", they will be seen as the same port by HDL Bencher. This causes errors.
Solution
In order to avoid this naming conflict, simply rename one of the modules
Was this Answer Record helpful?
AR# 12051
Date
12/11/2006
Status
Archive
Type
General Article
By using this website, I accept the use of cookies.
Learn more