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AR# 12062

Schematic - How do I pass a generic map attribute to a VHDL macro in a schematic?

Description

Keywords: ECS, generic, map, attribute, pass, ISE

VHDL macros can be constructed using generic statements to allow multiple instances of the macro to be placed with different constant values. How do I use the generic map attribute in ECS?

Solution

To use a generic map attribute in the schematic editor, you must place the generic attribute into the following three locations:

- In the entity declaration of the VHDL macro component
- In the component declaration (in the macro symbol)
- In the component instantiation (on an instance of the macro symbol)

To place the generic attribute in an entity declaration, enter the attribute's name, type, and default value.

Example:
entity my_HDL_Macro is
generic (gen_const : std_logic_vector(3 downto 0):="0000");
port(
.
.
.

To place the generic attribute in the component declaration (in the macro symbol):

1. Edit the symbol by right-clicking it and selecting Symbol -> Edit Symbol.
2. Select Edit -> Object Properties, and select "New".
3. Enter the generic attribute's name in the Attribute Name field ("gen_const" in the example above).
4. Leave the Attribute Value field blank.
5. Choose the applicable Attribute Value Type. If the correct type is not listed, choose "User". For the example above, use bit_vector.
6. Click OK to close the New Attribute window.
7. Select the newly created attribute and click Edit Traits.
8. If you selected "User" as the type in the User Type Name box, enter the desired type ("STD_LOGIC_VECTOR" would be entered for the example above).
9. Highlight the VHDL category and select "Write this Attribute:" and "1. In a generic map statement".
10. Click "OK" to accept your choices.
11. Save the symbol and close.


To place the generic attribute in the component instantiation (on an instance of the macro symbol):

1. In the schematic file, right-click Instance and Select Object properties, and select New.
2. Enter the generic attribute's name in the Attribute Name field ("gen_const" in the example above).
3. For the Attribute Value, type "0101" (or the specific value that you wish to pass).
4. Choose the applicable Attribute Value type. If the correct type is not listed, choose "String" as the type. (This allows double-quotation marks to be placed on the given value.)
5. Select OK to close the New Attribute window.
6. Select the newly created attribute and click Edit Traits.
7. Highlight the VHDL category and select "Write this Attribute:" and "1. In a generic map statement".
8. Click OK to accept your choices, and save the schematic.

NOTE: The schematic entry tool does not support passing generic values to submodules to define port widths. The tool will only use the generic default to determine the port width for the instantiated modules.
AR# 12062
Date Created 08/29/2007
Last Updated 12/23/2008
Status Active
Type General Article