How do I simulate JTAG pins using the Xilinx IBIS models?
Use the IBIS models provided by Xilinx, with the following settings, to simulate the JTAG TAP pins (TDI, TDO, TMS, TCK):
I/O Standard => LVTTL
Drive Strength => 12 mA
Slew Rate => Fast
Other than Virtex-II Pro and Spartan-3, these settings also apply to unconfigured I/Os during EXTEST and SAMPLE/PRELOAD. After configuration, use the IBIS models with the I/O standard, drive strength, and slew rate that have been specified in the user design. For Virtex-II Pro and Spartan-3, use LVCMOS25, 12 mA, and fast slew rate.